职位描述
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Job Description:
Intel labs is a world class research lab with the mission to drive research
and development of innovative technologies. In this position of ASIC backend
design lead, you will be in Intel labs China one of the top branches in Intel
labs, will be responsible for SOC architect. You will also work very closely
with designer and verification lead for given design.
Qualifications:
Minimum qualifications are required to be initially considered for this
position. Preferred qualifications are in addition to the minimum requirements
and are considered a plus factor in identifying top candidates. Minimum
Qualifications: ? BE or equivalent degree? 5-8 years high performance SOC
architect experience? Experience in high performance or lower power ASIC design
include CPU, DSP, or other ? Experience in SoC development lead role. Familiar
with modern SoC challenges in terms of power, performance, complexity, and cost
tradeoffs.? Experience in the whole design flow of SOC chips,? Expertise in SoC
integration of various subsystems and peripherals? Familiar with the industry's
commonly used on-chip interconnect NoC technology, IO interface protocols
(DRAM, PCIE, etc.) and hybrid memory system principles, with relevant IP usage
experience preferred;? Fluent in RTL design using Verilog and experience with
simulators and waveform debugging tools. ? Strong project management skills and
the ability to drive teamwork internally and externally? Good spoken and
written English.Preferred Qualifications: ? Experience of CPU architect ?
Experience in designing larger scale chips or core complex module
architectures? Experience with the common low-power design and verification
process in the industry? Experience of a large-scale SOC design verification is
a plus? Successful tape-out experience of CPU, GPU, or any complex SoC highly
desirable? Experience of custom design ? Master in CS or EE
Intel labs is a world class research lab with the mission to drive research
and development of innovative technologies. In this position of ASIC backend
design lead, you will be in Intel labs China one of the top branches in Intel
labs, will be responsible for SOC architect. You will also work very closely
with designer and verification lead for given design.
Qualifications:
Minimum qualifications are required to be initially considered for this
position. Preferred qualifications are in addition to the minimum requirements
and are considered a plus factor in identifying top candidates. Minimum
Qualifications: ? BE or equivalent degree? 5-8 years high performance SOC
architect experience? Experience in high performance or lower power ASIC design
include CPU, DSP, or other ? Experience in SoC development lead role. Familiar
with modern SoC challenges in terms of power, performance, complexity, and cost
tradeoffs.? Experience in the whole design flow of SOC chips,? Expertise in SoC
integration of various subsystems and peripherals? Familiar with the industry's
commonly used on-chip interconnect NoC technology, IO interface protocols
(DRAM, PCIE, etc.) and hybrid memory system principles, with relevant IP usage
experience preferred;? Fluent in RTL design using Verilog and experience with
simulators and waveform debugging tools. ? Strong project management skills and
the ability to drive teamwork internally and externally? Good spoken and
written English.Preferred Qualifications: ? Experience of CPU architect ?
Experience in designing larger scale chips or core complex module
architectures? Experience with the common low-power design and verification
process in the industry? Experience of a large-scale SOC design verification is
a plus? Successful tape-out experience of CPU, GPU, or any complex SoC highly
desirable? Experience of custom design ? Master in CS or EE
工作地点
地址:北京海淀区海淀区科学院南路2号融科资讯中心A座
![](http://img.jrzp.com/jrzpfile/cityrcw/SearchJob/images/jg.png)
![](https://img.jrzp.com/images_server/comm/nan.png)
职位发布者
Auro..HR
英特尔(中国)研究中心有限公司
![](http://img.jrzp.com/jrzpfile/cityrcw/images/sfrz_yrz.png)
-
IT服务·系统集成
-
200-499人
-
外商独资·外企办事处
-
海淀区科学院南路2号融科资讯中心A座8层
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